Semiconductor technology has shown a general trend towards dramatic increases in integrated circuit speed and density. Both of these trends are facilitated by an overall reduction in device (circuit element) geometries (sizes). As semiconductor circuit elements become smaller, the distances between them on a semiconductor die become smaller, and parasitics (such as parasitic capacitances) and switching currents become smaller. In technologies such as CMOS, where overall current draw and switching speed characteristics are dominated by the effects of parasitics, the result is a reduction in total power consumption at the same time as switching speed is improved. Overall speed is further improved by the reduction in signal propagation time between active devices (e.g., transistors) resulting from the shorter distances involved. Nevertheless, in high speed integrated circuitry based on sub-micron geometries, delays in the tens or hundreds of picoseconds can be appreciable.
In order to minimize the length of wiring between semiconductor devices, a technique generally known as "flip chip" mounting is employed. A number of patents show that a semiconductor die (or "chip") can be "flip-chip" mounted and connected to another die (or "substrate") via a pattern or array of conductive bumps disposed on a surface of a semiconductor die, or on both the die and an underlying substrate. For example U.S. Pat. Nos. 4,825,284 and 4,926,241, incorporated by reference herein, describe methods for "flip-chip" mounting of a semiconductor die to a substrate by means of conductive (solder) bumps. Typically, the conductive bumps are ball-like structures formed of solder and disposed in a pattern on a surface of the die. A mating pattern of bond pads and/or similar conductive bumps is disposed on a surface of the underlying substrate. The die is positioned over the substrate and the conductive bumps on the die are "re-flowed" or otherwise fused to their counterpart connection elements on the surface of the substrate to form both electrical and mechanical connections between the die and the substrate.
Similar techniques are known in the art for mounting a semiconductor device package to a printed circuit board or other substrate, although they tend to be on a larger scale than the techniques for mounting a semiconductor die to a substrate. U.S. Pat. Nos. 4,700,276, 5,006,673, and 5,077,633, incorporated by reference herein, are generally directed to such techniques. Semiconductor devices employing conductive bumps are commonly referred to as "pad array chip carriers", or as "bump grid arrays". Other references to pad array chip carriers and similar mounting techniques are found in "Pad Array Improves Density" (Electronic Packaging and Production, May 1992, p. 25.), "Overmolded Plastic Pad Array Carriers (OMPAC): A Low-Cost, High Interconnect Density IC Packaging Solution for Consumer and Industrial Electronics", (Freyman and Pennisi, IEEE Publication No. 0569-5503/91/0000-176, 1991), and "LED Array Modules by New Technology Microbump Bonding Method" (Hatada, Fujimoto, Ochi, Ishida, IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. 13, No. 3, Sep. 1990, pp. 521-527). A related mounting scheme is disclosed in U.S. Pat. No. 4,717,066, incorporated herein by reference, wherein a gold alloy is used for the conductive bumps (balls) rather than solder.
Hereinafter, all conductive bump connection techniques, both for chips (semiconductor dies, e.g., "flip-chip" mounting) and packaged semiconductor devices (e.g., pad array chip carriers) will be referred to collectively as "bump bonding", and the resulting assembly of one element to another will be referred to as a "bump-bonded assembly".
Generally, as used herein, a bump-bonded assembly includes one or more relatively small silicon chips (or packages) mounted in face-to-face relationship to a larger silicon chip, package, or substrate. Solder balls are formed on the opposing faces of the chips (or packages) and the substrate, at a number of positions corresponding to one another. In other words, the pattern and spacing of the solder balls on the chip (or package) match the pattern and spacing of solder balls on the substrate. Generally, for bump bonding semiconductor dies, the conductive bumps are arranged around a peripheral area of the die, although locating bumps in a central area of the die is also possible. The chip (or package) is brought into face-to-face relationship with the substrate, and with the solder balls of the chip (or package) aligned with the solder balls of the substrate. The chip (or package) and substrate are subjected to heat, which (ideally) causes the solder balls of the chip (or package) to fuse with the corresponding solder balls of the substrate, thereby forming solder joints between the chip and the substrate.
When using bump bond technology, there are significant reliability issues associated with the bump breaking in use. It is widely known in the art that conductive bump connections between a die and a substrate may (and often will) break because of differences in rates of thermal expansion between the die and the substrate. Thermally induced mechanical stresses at the conductive bump bonds can build up to a point where the mechanical structure of the conductive bump fails and the bump breaks or is "torn" away from the die.
Although this failure mechanism is well documented, it is by no means the only failure mechanism. Stresses on conductive bumps caused by mechanical shock of moderate values (50-100 g's) can easily exceed the strength of the bump bond connections. In the absence of completely uniform distribution of stress over the array of solder bumps, individual conductive bumps can easily be broken, or torn away from the die, by stresses of this magnitude.
When added to the probability of thermally-induced bump bond failures, the probability of mechanical shock-induced bump bond failures augments the overall problems associated with bump bonding, and makes conventional bump bonding techniques unsuitable for many harsh environments (e.g., many automotive, aircraft and military applications) without some auxiliary means of limiting mechanical shock.
One possible approach to preventing mechanical shock-induced failures of bump bonds is to anchor the die firmly to the substrate in the process of forming bump bond connections, for example, via a die attach structure (e.g., a planar "spacer" between the die and substrate to which both are firmly attached). For example, commonly-owned U.S. Pat. No. 5,111,279, incorporated by reference herein, discloses a preformed planar structure interposed between a chip and a substrate which is formed of materials which will tend to draw the chip towards the substrate. In this manner the die is secured and prevented from converting mechanical shock into shear forces at the bump bond connections. Unfortunately, however, this may exacerbate the problem of alleviating thermally induced stresses within the die itself, and thermal mismatches between the die and the substrate. Since the die is now firmly mounted to the substrate (via the planar spacer), any stresses due to thermal coefficient mismatch are transmitted directly to the die, creating a risk of fracturing the die.
Further, thermal coefficient mismatch with the die attach structure can create additional thermally-induced stress problems. For example, as the die attach structure (interposed between the die and the substrate) is subjected to thermal changes, it may expand at a different rate in the vertical direction (i.e., in the die-to-substrate direction) than the bump bond connections (e.g., solder joints). As a result, the die attach structure can create a situation where the bump bond connections are literally being pulled apart by the thermal expansion of the die attach structure.
The die can be cooled to reduce thermally induced stresses, both at the bump bond connections and within the die itself. Conductive cooling via heat-sink structures can be used, but this approach tends to be bulky and expensive. Many active approaches to cooling are known in the art, including fan-forced gas (e.g., air) cooling whereby a flow of a cooling gas is directed at or around the die. A die attach structure, depending upon the material used, can provide some conductive cooling. However, a die attach structure interposed between the die and the substrate, particularly a planar structure interposed between the die and the substrate, tends to limit gas or fluid-based cooling in the die by preventing gas or fluid flow between the die and the substrate. This can be particularly troublesome in multi-tier stacked flip-chip assemblies where some dies may have very little exposed surface area.
What is needed is a die attach structure, suitable for interposition between a die (e.g., a semiconductor chip or package) and a substrate (e.g., another semiconductor chip or a printed circuit board), which mechanically joins the chip to the substrate without augmenting thermal stress problems of the assembled chip and substrate, and which facilitates cooling of the die.